Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include these exemplary devices, as well as encompass other devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
There are many known forms of error-correction codes. One known type of error-correction code is a Turbo Code. Turbo Codes use convolutional encoding. Turbo Codes are becoming more popular owing to their ability for forward error correction. However, effective forward error correction comes at a price of computational complexity. A bottleneck of this computational complexity generally occurs at a conventional Add-Compare-Select-Offset (“ACSO”) unit or a conventional Add-Compare-Select (“ACS”) unit of a Turbo Code decoder. Thus, the conventional ACSO or ACS unit may be part of what is generally known as a “critical path” or “speed limiting path” of a Turbo Code decoder.
Accordingly, it would be desirable and useful to provide an improved ACSO or ACS unit to enhance the speed of operation or reduce the size of a Turbo Code decoder.